ASIC and FPGA implementations of H.264 DCT and quantization blocks
Roman C. Kordasiewicz, Shahram Shirani · 2005
In the search for ever better and faster video compression standards H.264 was created. With it arose the need for hardware acceleration of its very computationally intensive parts. To address this need, this paper proposes two sets of architectures for the integer discrete transform (DCT) and quantization blocks from H.264. The first set of architectures for the DCT and quantization were optimized for area, which resulted in transform and quantizer blocks that occupy 294 and 1749 gates respectively. The second set of speed optimized designs has a throughput anywhere from 11 to 2552 M pixels/s. All of the designs were synthesized for Xilinx Virtex 2-Pro and 0.18/spl mu/m TSMC CMOS technology, as well as the combined DCT and quantization blocks went through comprehensive place and route flow.