A modified clock scheme for a low power BIST test pattern generator
Patrick Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, Hans-Joachim Wunderlich · 2002
In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.