Design of novel CAM core cell structures for an efficient implementation of low power BCAM system
Manikandan Palanichamy, Bjørn B. Larsen, Einar J. Aas · 2009
This paper presents novel cell structures for fully parallel static type binary content addressable memory (BCAM) with low power and high flexibility. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the word match line (ML) structure of low power BCAM employs Static pseudo CMOS (SPC) logic. HSPICE simulations for 32×32 and 128×32 BCAM systems were performed under 0.18 mm technology for different cell structures. The result shows that the proposed design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns @ 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM show that the proposed BCAM cell reduces power dissipation by 76% and improves search speed by 65%