VLSI architecture for template matching
C. Chakrabarti, Joseph F. JáJá · 2002
A systolic architecture for computing real-time template matching is presented. The architecture consists of a multiplier-accumulator and shift registers. The architecture achieves optimal speedup with simple data and control flow. The I/O bandwidth problem is handled by storing part of the input image in the shift registers and by circulating the shift registers so that the processor array can compute on the same input many times.>