A high efficient multiplier for the RS decoder
Jyh-Horng Jeng, Jyh-Ming Kuo, T.K. Tnuong · 2003
The field element multiplication plays an important role in the VLSI implementation of an RS decoder. In this paper, a high efficient multiplier is derived, which removes all the redundant computations. The fast multiplier uses only 64 AND gates and 83 XOR gates, and the total gate delay is 6.