Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test
Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li · 2009
The self wide-range (26%~76%), fine-scale (34 ps) duty cycle adjustment technique with high-precision (28 ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.