Fully parallel 30-MHz, 2.5-Mb CAM
F. Shafai, Kenneth J. Schultz, G.F.R. Gibson, Andreas Bluschke, D.E. Somppi · IEEE Journal of Solid-State Circuits · 1998
Translation functions in high-speed communications networks such as Internet protocol and asynchronous transfer mode are requiring larger and faster lookup tables. Content addressable memories (CAMs) provide built-in hardware lookup capability with high speed and high flexibility in address allocation. Previous high-capacity CAMs have been inadequate for emerging applications; comparators are time-shared among multiple bits or multiple words, resulting in serialized operation, Fully parallel architectures represent the best solution for high-speed operation, but previous fully parallel CAMs have lacked the capacity required for leading-edge networking applications. This paper describes a fully parallel (single-clock-cycle) CAM chip. The chip uses a 0.35-/spl mu/m digital CMOS technology to achieve 2.5 Mb of CAM storage and 30-MHz operating frequency. Innovative layout techniques are used to achieve two-dimensional decoding, a traditional problem with high-capacity CAMs. Architecture and operation of the chip are described, including a novel NAND match architecture, operation-specific self-timing loops, and on-board cascade management circuits. The chip functions at 31 MHz, with a search access time of 26 ns and an average search power dissipation of 5.2 W at 25 MHz.