A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
Roberto Sarmiento, F. Tobajas, Valentin De Armas, Roberto Esper-Chain, Jose Fco. Lopez, Juan Antonio Montiel-Nelson, A. Nunez · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1998
In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.