Designing dedicated parallel architectures with Petri nets
Werner B. Joerg · 2003
A subclass of Petri nets is identified, amenable for direct casting into silicon, and is extended for incorporation into a practicable design process for parallel structures on single chips. The performance of the nets derived through this process can be tuned to given speed or area requirements by folding. Basic folding techniques are introduced. The result is an asynchronous reconfigurable network of heterogeneous processing elements that can execute in parallel. For implementation a netlist description of the network is fed to conventional VSLI design tools.>