Chip level power supply partitioning for I/sub DDQ/ testing using built-in current sensors
A. Prasad, D.M.H. Walker · 2004
The International Technology Roadmap for Semiconductors projects that I/sub DDQ/ levels will rise rapidly with each technology node. In addition, manufacturing variations in the I/sub DDQ/ level will be difficult to control. This combination will make it increasingly difficult to distinguish defect-free from defective chips via I/sub DDQ/ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free I/sub DDQ/ level. In the future, such a scheme would require 100000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to carry out this power supply partitioning.