FPGA digital down converter IP for SDR terminals
Gianmarco Girau, Maurizio Martina, Andrea R. Molino, Andrea Terreno, F. Vacca · 2003
During the past years, software platforms have proved a superior scalability with respect to hardware solutions. However, wireless communication rates can not be faced resorting only to software. Software defined radio paradigm will try to push reconfigurable blocks as near as possible to the antenna. The first block suitable in this implementation is the digital down converter, needed to adapt higher antenna's data rate to intermediate frequency ones. In this paper a fully reconfigurable IP of a cascaded integrator comb (CIC) filter, an economical class of multiplier-less filters, is proposed. FPGA implementation has lead to very satisfactory results: 135 MHz on a XCV100E.