A retention-aware test power model for embedded SRAM
Baosheng Wang, Josh Yang, Yuejian Wu, A. Ivanov · 2005
This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a single-rectangle power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of zero power consumption for the detection of Data Retention Faults. This paper takes advantage of this zero power period and proposes a retention-aware test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarious in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the zero power period is fully utilized in a SoC environment.