A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability
Rakesh H. Patel, Myron Wong, J. Costello, D. Reese, V. Bocchino, M. Chu, J. Turner · 2002
This paper discusses a complex programmable logic device which provides up to 12,000 usable gates. The EPM9560 is the first member of the third-generation MAX 9000 family. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 560 product term based macrocells and circuit techniques to achieve an overall 90.7 MHz system operating frequency. The device is designed to operate in a 3.3 V or 5 V systems. It has built-in JTAG boundary scan for improving testability and in-system programmability for ease of manufacturing.