A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU
Masao Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, K. Ohno, Masahito Saigusa, Minoru Sakata, Yukio Kodama, Yuji Arai, Teruyoshi Komuro · 2008
The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds of media IPs; and the interconnect buffer (ICB) extends its function to involve the IP-MMU.