A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store
Jiro Miyake, T. Maeda, Y. Nishimichi, J. Katsura, T. Tainguchi, S. Yamaguchi, Hisakazu Edamatsu, S. Watari, Yuji Takagi, Kosuke Tsuji, Shigeo Kuninobu, S. Cox, D. Duschatko, Doug MacGregor · 1990
A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using a data-flow clocking scheme. A floating-point unit performs single- and double-precision floating-point operations concurrently with an integer unit. The chip is fabricated using 0.8- mu m double-metal CMOS technology. About 1M transistors are contained in the 14.85*15. 13-mm die housed in a 238-pin pin-grid array (PGA).>