Hierarchical LVS based on hierarchy rebuilding
Wonjong Kim, Hyunchul Shin · 1998
A new hierarchical layout vs. schematic (LVS) verification system has been developed for layout verification. It compares a hierarchical schematic netlist and a flattened layout netlist. The schematic hierarchy is restructured for consistent hierarchical matching and then the same hierarchy is built from the layout netlist. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm. Each subcircuit is found from the layout by using a modified SubGemini algorithm in bottom-up fashion. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage.