Behavioural description and VLSI verification
George J. Milne · IEE Proceedings I Solid State and Electron Devices · 1986
Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioural description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, they also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.