Bridge: a behavioral synthesis system for VLSI
Chia-Jeng Tseng, Ruey-Sing Wei, S.G. Rothweiler, M.M. Tog, A.K. Bose · 2003
Bridge is a behavioral synthesis system in which a variable in a behavioral description can be either a storage element or a signal. The impact of treating a variable as a signal on lifetime analysis is discussed. The feature of supporting both signals and registers for program variables facilitates systematic tradeoffs between cost and performance. Intelligent bindings of the variables in a behavioral description to registers and signals not only reduce the implementation cost but also improve the circuit performance. Experimental data for the descriptions of three telecommunication circuits are presented.>