A fair queueing architecture for ATM switches with input buffers
Y. Shimojo · 2002
The available bit rate (ABR) and unspecified bit rate (UBR) are reservationless service categories at the ATM layer. ATM switches are required to have large cell buffers to provide such services. A new queueing architecture named Kago for the large input buffer switch is proposed. Kago provides per-VC fair scheduling among the multiple input buffers. The mechanism is divided among several blocks, and is executed in a distributed manner. The volume of processing by each block has little dependence on the number of input buffers and the number of VCs. From the simulation results, it is shown that each VC obtains fair bandwidth regardless of its input port.