114 MFLOPS logarithmic number system arithmetic unit for DSP applications
David M Lewis · IEEE Journal of Solid-State Circuits · 1995
An arithmetic core for DSP applications, comprising two multiplier/dividers and an adder/subtractor, using logarithmic number system (LNS) arithmetic, is described. For most operands, precision better than the worst-case precision of IEEE 754 is obtained. Three operations per cycle are performed using 69k transistors integrated in a 16 mm/sup 2/ core in 1.2 /spl mu/m CMOS, offering better performance than the best previous result in only 43% of the area. The use of a new interleaved memory ROM structure and a second-order function interpolator are the key techniques that result in reduced area. This modest area allows several core units to be integrated on a chip for high performance DSP applications.