A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems
J. Korematsu, T. Ueda, M. Matsuo, Kazuki Tani, Naoto Okumura, Koichi Ishimi, T. Yoshida, Yuichi Saito, J. Hinata · 2002
This paper describes a 32-bit superscalar microprocessor G/sub MICRO//400, based on the TRON architecture specifications. The G/sub MICRO//400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as frame buffer or character-strings, the G/sub MICRO//400 has improved the execution efficiency of multiple-operation instructions by block-data-transfer and 64-bit processing. In order to improve the task switching latency, the on-chip caches are used as a local memory in which the context blocks are stored. These techniques are suitable for realtime embedded systems, such as X-window terminals and printers. Using 0.5 /spl mu/m triple-layer metal CMOS technology, the G/sub MICRO//400 integrates 1485K transistors on a 108 mm/sup 2/ die area. The G/sub MICRO//400 achieves a processing speed of 45 MIPS at 40 MHz.>