Design of 128QAM channel equalizer in FPGA
Bin Du, Zhiming He · 2012 International Conference on Computational Problem-Solving (ICCP) · 2012
In All-digital IF receiver, the timing synchronization signal, due to inter-symbol interference will produce a high error rate, and then through the equalizer, eliminate inter-symbol interference. This paper uses CMA (constant modulus algorithm) to eliminate inter-symbol interference, and uses pipeline structure and complex multiplication optimization to improve processing speed, and save resources of FPGA.