A 0.8 μ 100-MHz 2-D DCT core processor
Yi-Feng Jang, Jinn-Nang Kao, Jinn-Shiang Yang, Po-Chuang Huang · IEEE Transactions on Consumer Electronics · 1994
The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG.>