Prototype testing of high-speed CMOS digital circuits
Volker Schindler · 1996
A circuit allowing easy prototype testing of high-speed CMOS digital logic has been constructed and successfully fabricated. It acts as an on-chip interface between a high-speed circuit and a chip-tester that is generally used for evaluation purposes. Although only 4 off-chip interconnection lines are needed to control/observe one test circuit data signal, the maximum frequency of the test circuit may be determined without altering the off-chip frequency. Fabricated circuits were measured to work up to 170 MHz with a sample circuit to be tested, using a 0.8 /spl mu/m standard CMOS process technology. The main part of the circuit is given by a gated oscillator performing a clock multiplication by 4, which has been verified by e-beam measurement to operate up to 440 MHz.