Concurrent testing in high-level synthesis
Ravibala Singh, John P. Knight · 1994
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit concur-rently with its rwrmal operation. Themethod tests hard-ware elements when they are not in use in the data-jlow graph. An algorithm for synthesizing the test circuit is pre-sented that starts with the data-jlow graph, generating a circuit to cycle test vectors through the idle hardware and produce a signature so as to give a built-in-self-test. By utilizing idle computational time for testing, the method reduces test-time overheads. 1.0 Concurrent testing and applicability of the test method At the present time, many ICS are tested only by pro-duction tests at the factory. More rccentl y some circuits have used built-in self-test. This makes production test-ing easier and also allows them to be tested in the field by service personnel during “power up ” or even tested remotely over telephone lines. Concurrent tests can be run at the same time that the circuit is processing data. This allows testing of circuits that run continuously, as in tele-phone central offices, air-traffic control systems, or pro-duction control systems. Concurrent testing can also give a faster warning if a system develops a fault. A machine tool control, for example, may be changed to a “safe ” mode if a fault is detected. Concurrent testing is also a practical way to detect soft errors, such as caused by power glitches, metastability, electromagnetic transients, or leaky dynami-c RAMS. The test method presented here is a concurrent, built-in self-test which can be incorporated into the dab-paths yn-thesis process. Testing of a circuit is time-shared with the