A high-speed real-time binary BCH decoder
Shyue‐Win Wei, C.-H. Wei · IEEE Transactions on Circuits and Systems for Video Technology · 1993
A high-speed real-time decoder for t-error-correcting binary BCH codes based on a modified step-by-step decoding algorithm is presented. The average operation cycle, for decoding each received word is just equal to the block length of the codeword. The decoder is constructed of three modules: the syndrome module, the comparison module, and the error corrector. Since all of the modules can be implemented by systolic circuits, the data rate of this decoder can theoretically be up to the rate of the inverse of two logic-gate delays operating from approximately several hundreds of megabits per second to the order of gigabits per second. Thus, the decoder can be applied in broadband service and video processing. By avoiding inverse operations in the step-by-step decoding method, the circuit complexity of the decoder can be made much less than that of the standard algebraic method. The detailed circuit diagrams of the comparison module and error corrector for double- and triple-error-correcting binary BCH codes are given for illustration.>