A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study
Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang · 2008
This paper presents a new tool for SystemVerilog RTL modifications with on-the-fly validation of local RTL changes. The tool, SV-rewrite, imports an initial version of SystemVerilog RTL and elaborates it into a hierarchical design description visualized as structural diagrams. From the design cockpit the user can select any set of visualized components, open a favorite text editor, modify then validate the new RTL description, and finally substitute this new rewritten RTL into the larger model to replace the originally selected components. This process of local validated rewrites can be repeated until the entire RTL is safely rewritten. We studied RTL abstraction using SV-rewrite to abstract the Pentium 80602 (P54CS) integer execution unit and register file. We have produced a significantly more readable RTL that is 2 to 3 times smaller than the original one. The abstracted RTL was validated by booting Linux on an FPGA-based emulation platform.