VLSI design of a one-chip data-driven processor: Q-v1
Hiroaki Terada, Hiroshi Nishikawa, Katsuhiko Asada, S. Matsumoto, Souichi Miyata · Fall joint computer conference · 1987
This paper describes the VLSI design considerations and basic hardware structure of a one-chip data-driven processor Q-v1 which can process high flow-rate data-streams in a dynamic mode of execution. Since the Q-v1 is primarily designed to be a functional VLSI component that is easily programmable to perform various dedicated processing functions, special design considerations were used to realize high on-chip data-flow capability by extensive utilization of an elastic pipeline structure. This paper first presents a dynamic mode data-driven execution-scheme with special emphasis on general design considerations for VLSI-oriented implementation. This paper also presents the Q-v1's basic self-timed elastic data-transfer mechanism. Its application to various functional modules gives rise to a unique “flow-thru processing” concept. That is, all processing, associative and selective packet-transfer functions are carried out in a highly parallel fashion by the elastic packetized data-flows through distributively and autonomously controlled elastic pipelines.