LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits
Sen-Chung Jiang, Chung Len Lee, Wen-Zen Shen, J.-E. Chen, Ching-Ping Wu · International Symposium on VLSI Technology, Systems, and Applications · 2003
An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.>