Block implementation of half-plane digital filters
Ramachandran Gnanasekaran · IEEE Transactions on Circuits and Systems · 1987
This communication deals with the derivation of a block implementation equation for asymmetric half-plane digital filters. First, a half-plane block transformation concept is developed which is essentially a matrix formulation for the computation of the products of two-sided polynomials and one-sided power series. Using this, a basic block equation is derived for the half-plane digital filters. It is also reasoned that the block computation of half-plane filters can be accomplished only in terms of blocks of samples in a row or a column, as opposed to the computation in terms of subarrays in the case of quarter-plane filters.