A novel storage scheme for parallel turbo decoder
Xiang He, Hanwen Luo, Haibin Zhang · 2006
In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme borrows its idea from vertex coloring in graph theory. Compared to similar method which also uses un-natural order in storage(2), our scheme requires more memory blocks but allows a simpler configuration method when code length changes, which can be implemented on-chip. The major bottleneck of our scheme is interconnection (3) since it doesn't put any constraint on interleaver. However, experiment shows, for a moderate decoding throughput(40~50M bits/sec), the hardware cost is still affordable with 3GPP's interleaver(4), 5 iterations and 80~100MHz system clock. Keywords-parallel turbo decoding; vertex coloring; I. MEMORY MULIPLE ACCESS PROBLEM During FPGA implementation of turbo decoder, a substantial amount of memory is assigned to store channel information and extrinsic information. A decoder using parallel MAP algorithm contains multiple soft-input-soft-output modules (SISO) (1), so parallel access to these storages is required. When translated into hardware design it means that data required by different SISOs at the same time must not be stored in the same RAM block. Fig.1(a)(b) illustrates memory access during one iteration in turbo decoding, which is conceptually divided into 2 phases: (a) decoding against the 1 st component code, and (b) decoding against the 2 nd component code. During each phase, the trellis of the component code is divided into three segments, each taken cared of by one SISO module. Suppose we avoid memory access contention in the 1 st