RTL Test Point Insertion to Reduce Delay Test Volume
Kedarnath J. Balakrishnan, Lei Fang · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2007
In this paper, a novel test point insertion methodology is presented for RTL designs that aim to reduce the data volume of scan-based transition delay tests. Test points are identified based on functional information of RTL primitives using a satisfiability based algorithm. A subset of scan flip-flops is identified for conversion to enhanced-scan, i.e., the values are stored in two flip-flops thereby removing the circuit dependency of the second pattern in broadside transition tests. Using the proposed methodology, the number of specified bits required to test transition faults is reduced thus improving test set compaction. The advantage of test point insertion at RTL is that the extra delay due to multiplexers can be absorbed during logic synthesis. Experimental results show that the proposed methodology can reduce transition test data volume by more than 30% with 1% area overhead and without violating timing constraints.