Sparcle: an evolutionary processor design for large-scale multiprocessors
Anant K. Agarwal, John D. Kubiatowicz, David A. Kranz, Beng-Hong Lim, Donald Yeung, Gabriel Sebastian D’Souza, Michael Parkin · IEEE Micro · 1993
The design of the Sparcle chip, which incorporates mechanisms required for massively parallel systems in a Sparc RISC core, is described. Coupled with a communications and memory management chip (CMMU) Sparcle allows a fast, 14-cycle context switch, an 8-cycle user-level message send, and fine-grain full/empty-bit synchronization. Sparcle's fine-grain computation, memory latency tolerance, and efficient message interface are discussed. The implementation of Sparcle as a CPU for the Alewife machine is described.>