Timed pattern generation for noise-on-delay calculation
Seung Hoon Choi, Kaushik Roy, Florentin Dartu · Proceedings - ACM IEEE Design Automation Conference · 2002
Computing the noise on delay effects is required for all circuits from simple ASIC designs to microprocessors. Transistor-level simulation engines make accurate delay calculation affordable only if the number of simulation per stage is very small. We propose a solution that predicts the alignment of aggressor signals with respect to the victim signal to induce the worst-case noise effect on delay. The aggressor alignment can be used to setup a detailed simulation. The worst-case delay in the presence of noise is predicted within 5% error for more than 99% of the cases tested using an average of 1.27 simulations per stage transition.