Multiple Fault Models for Timed FSMs
Samrat S. Batth, M. Ümit Uyar, Yu Wang, Mariusz A. Fecko · 2006
An implementation under test (IUT) can be formally described using finite-state machines (FSMs). Due to the presence of inherent timing constraints and variables in a communication protocol, an IUT is modeled more accurately by using extended finite-state machines (EFSMs). However, infeasible paths due to the conflicts among timing condition and action variables of EFSMs can complicate the test generation process. The fault detection capability of the graph augmentation method given in [8], [9] is analyzed in the presence of multiple timing faults. The complexity increases with the consideration of the concurrent running and expiring of timers in a protocol. It is proven that, by using our graph augmentation models, a faulty IUT will be detected for the multiple occurrences of pairwise combinations of a class of timing faults.