LSSD COMPATIBLE AND CONCURRENTLY TESTABLE RAM
H. Maeno, Koji Nii, S. Sakayanagi, S. Kato · 2005
Design-for-testability of ASICs has become complex because of embedded RAMs. This paper presents a design methodology for testing embedded RAMs. This methodology is based on scan design, but a remarkable reduction of test vectors for RAMs can be achievcd by using exhaustive random pattern for addressing and a newly designed scan register for data compression. A RAM test circuitry which realizes concurrent testing of multiple RAMs by using this new scan register is presented.