BISTSYN-a built-in self-test synthesizer
C.-I.H. Chen · 2002
The author presents a unifying procedure, called three phase cluster partitioning (TPCP), for automated synthesis of a pseudo-exhaustive test generator for built-in self-test (BIST) design. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive testing. A design generator named BISTSYN, based on the TPCP algorithm, was developed and implemented to facilitate the BIST design with this methodology. The input to the design generator can be a circuit description at the gate level which is viewed as a netlist or the circuit output functional dependency sets. BISTSYN provides the BIST mechanisms as the output. The hierarchical design procedure is computationally efficient and produces test generation circuitry with lower hardware overhead and fewer pseudo-exhaustive test patterns than existing techniques.>