High performance VLSI implementation for H.264 Inter/Intra prediction
Mythri Alle, Jayanta Biswas, S. K. Nandy · 2007
We provide a hardware realization of motion compensation and reconstruction (MCR) module for H.264 baseline profile. We synthesize the MCR module using UMC library in 0.13 mu CMOS technology. Our implementation occupies an area of 94756 gates and operates at a frequency of 250 MHz.