Automatic signal processor code generation: matrix reduction based module optimization
T. Reichler, I.O. Hartimo, J. Jaatinen · 2002
An optimizing automatic code generator for a commercial target signal processor is described. The input to the system is an arbitrary graphical signal flow graph of the application which is converted to a set of linear equations. A number of matrix reduction steps are used to find the optimal order of the computational operations for digital signal processor implementation. This is converted into the assembler code for the TMS320C25 processor.>