Network topology exploration of mesh-based coarse-grain reconfigurable architectures
Nikhil Bansal, Sumit Kumar Gupta, Nikil D. Dutt, Alex Nicolau, Rajesh Gupta · 2004
Several coarse-grain reconfigurable architectures pro-posed recently consist of a large number of processing el-ements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these ar-chitectures: (a) changing the interconnection between PEs, (b) changing the way the network topology is traversed while mapping operations to the PEs, and (c) changing the communication delays on the interconnects between PEs. We propose network topology traversal strategies that first schedule PEs that are spatially close and that have more in-terconnections among them. We use an interconnect aware list scheduling heuristic as a vehicle to perform the net-work topology exploration experiments on a set of designs derived from DSP applications. Our experimental results show that a spiral traversal strategy, coupled with a two neighbor interconnect topology leads to good performance for the DSP benchmarks considered. Our prototype frame-work thus provides an exploration environment for system architects to explore and tune coarse-grain reconfigurable architectures for particular application domains. 1