A novel video signal processor with programmable data arrangement and efficient memory configuration
Yeong-Kang Lai, Liang‐Gee Chen, Hsu-Tung Chen, Mei‐Juan Chen, Yung-Pin Lee, Po-Cheng Wu · IEEE Transactions on Consumer Electronics · 1996
This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.