A low power GPS receiver architecture
Horng-Wen Lee, T.H. Meng · 2003
A low power GPS receiver architecture is proposed. Based on a code-phase estimation algorithm, the synchronization time for a GPS receiver can be reduced by 99%, thus allowing a relatively long power-down mode for low power operation. Depending on the actual user behavior, which is monitored by a self-regulated Kalman filter, the proposed GPS receiver can deliver continuous position fixes at the minimum power level.