A 100-MHz 64-tap FIR digital filter in 0.8- mu m BiCMOS gate array
T. Yoshino, Rajeev Jain, P.T. Yang, H. Davis, Wanda Gass, A.H. Shah · IEEE Journal of Solid-State Circuits · 1990
A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8- mu m triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm/sup 2/, which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible.>