Evaluation of fault tolerant technique based on homogeneous FPGA architecture
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi · 2012
FPGA fault detection consumes a great deal of test time compared with ASICs because FPGAs have complex structures. Re-placement and re-routing must be performed to avoid fault points, which causes an increase in recovery time and degrades performance. Therefore, we propose a fault detection method and develop placement and routing tools to avoid fault sources in tile and multiplexer level avoidance, respectively. In the evaluation, the detection method diagnosed a faulty multiplexer with six test configurations. We found that the performance of a faulty FPGA slightly decreased by 2% compared with a normal FPGA in multiplexer level avoidance.