A 400 megasample per second digital receiver ASIC
Robert Inkol, Valek Szwarc, L. Desormeaux, M.O. Esonu, D. Al-Khalili · 2002
An application specific integrated circuit has been designed to perform digital quadrature demodulation and other signal processing functions on digitized IF data in electronic warfare receivers. A fully pipelined, parallel architecture implemented on a GaAs gate array permits a nominal sampling rate of 400 megasamples per second. At this sampling rate the -3 dB bandwidth exceeds 80 MHz.