Special applications of the voting model for bridging faults
Steven D. Millman, John M. Acken · IEEE Journal of Solid-State Circuits · 1994
A transistor-level examination of bridging faults and the resulting logic-level bridging fault model is described. Experiments with simulations and silicon demonstrate its accuracy. Previous work has demonstrated the accuracy and efficiency of the voting model for bridging faults. This paper presents a complete formal description of the voting model. In addition, simple solutions to special applications of the voting model which generalize its applicability are presented. These applications include the Byzantine General's Problem, complex gate designs, and nonuniform transistor sizes. How to use Binary Decision Diagrams to compare the voting model to other fault models is also presented. Finally, delay tests are shown to be a poor means for detecting bridging faults. This work was done to show that the voting model, a logic-level model for bridging faults, accurately describes the behavior of real faults in real circuits.>