DIVA: dual-issue VLIW architecture with media instructions for image processing
Sang-Joon Nam, Young-Su Kwon, Yeon-Ho Im, Kyung-Ku Kang, Chong-Min Kyung · IEEE Transactions on Consumer Electronics · 1999
According to the demand on enormous multimedia data processing, we have designed a VLIW (very long instruction word) processor called DIVA (dual-issue VLIW architecture) exploiting the ILP (instruction-level parallelism) in multimedia programs. The DIVA processor which can execute two instructions in one cycle supports 86 instructions including 30 media instructions, and has a sub-word execution structure that supports the saturation mode arithmetic for image processing. Compared to scalar architectures without media instructions, the performance of the DIVA processor is improved by 2.2 to 5 times due to the combination of the VLIW architecture and media instructions. The DIVA processor, consisting of about 90,000 gates, was implemented using the 0.6 /spl mu/m CMOS SOG (sea-of-gate) process on a 8 mm/spl times/8 mm die, and has shown a performance of 80 MOPS (million operations per second) at 10 MHz clock frequency.