Formal verification of memory circuits by switch-level simulation
Randal E. Bryant · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1991
An N-bit RAM can be verified by simulating just O(N log N) patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator. By simulating many patterns in parallel, a massively parallel computer can verify a 4K RAM in under 6 min.>