Entity Overloading for Mixed-Signal Abstraction in VHDL
C.‐J. Richard Shi, C.‐J. Richard Shi · 1996
In this paper we propose to extend VHDL with entity overloading. With a minimal change to existing VHDL, entity overloading provides a strong support for mixed-signal, mixed-level, and mixed-domain abstractions. It is particularly promising in resolving some issues in VHDL-A language design. Furthermore, we illustrate that entity overloading can be combined with certain modeling rules to achieve polymorphic netlist.