FPGA implementation of a lossless to lossy bitonal image compression system
Andreas E. Savakis, Marcin Łukowiak, Jeremy Pyle · International Conference Mixed Design of Integrated Circuits and Systems · 2008
This paper presents an FPGA implementation of a lossless to lossy image compression system that incorporates region of interest processing. Block Arithmetic Coder Image Compression is combined with Low-Latency Greedy Flipping Utilizing Forgetful Error Diffusion for loss introduction. The system allows for perfect quality, associated with lossless compression, or three levels of reduced image quality, high, medium and low, associated with various levels of loss introduction. Region of interest processing can be incorporated by adjusting the system parameters for maximum visual benefit.